ULLAH, ANEES
Dependable System Design for Reconfigurable Safety-Critical Applications [Tesi di dottorato]
Politecnico di Torino, 2015

Scaling of transistor's channel length is entering the realm of atomic and molecular geometries making possible the design of powerful miniature sized computing device and enabling their omnipresence in every aspect of human life including safety-critical applications, for example, automotive, space and avionics and bio-medicine. However, these scaled nanoelectronic systems are increasingly vulnerable to transients and permanent faults posing severe threat to life and expensive equipment. Therefore, safety-critical applications should consider dependability from design, implementation, layout, fabrication to in-field operations. The evaluation of dependability of such systems is equally important. State-of-the-art SRAM-based FPGAs are interesting devices because they are not only the early adopters of latest technology nodes making them vulnerable to all sorts of nanoelectronic faults but their reconfiguration properties have potential counter-measure applications in dependable system design. This dissertation is focused on the usage of reconfiguration for improving and evaluating the dependability of nanoelectronic systems. The main research problem pursued in this work is the effective mitigation of soft errors like Single Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in FPGA's configuration memory, optimizing the reconfiguration times for fault injection and fault removal and emulation of permanent faults. To address these problems this work proposes solutions based on applying redundancy and reconfiguration at different levels of granularity leveraging the basic building blocks of FPGA's architecture and reconfiguration capabilities in an unconventional manner usually not supported by standard tools. The solutions presented effectively mitigate MBUs by using techniques of fine-grain and coarse-grain redundancy and reliability-oriented placement. Recovery times are optimized with fine-grain error detection, error localization and local repairing. The usage of carry-chain based error detectors promises very fast error detection times in orders of nanoseconds and has extremely low-area overhead. The programmable nature of LUTs is exploited for permanent stuck-at fault emulation of custom ICs using controlled LUT-mapping resulting in significant speed up against traditional fault simulation times.

diritti: info:eu-repo/semantics/restrictedAccess
In relazione con info:eu-repo/semantics/altIdentifier/hdl/11583/2592708
STERPONE LUCA
Settore ING-INF/05 - - Sistemi di Elaborazione delle Informazioni


Tesi di dottorato. | Lingua: Inglese. | Paese: | BID: TD18040841