Advanced methods techniques and digital architectures for high performance timing of events [Tesi di dottorato]
Politecnico di Milano, 2018-02-23

The precise measurement of time intervals is a primary goal in a growing number of applications and the challenge to achieve increasingly higher resolutions than ever is a main topic of research. In this sense, Time-of-Flight measurements and Time-Correlated Photon Counting are two milestones. Since the intrinsic resolution of the sensors used today is in the order of tens of picoseconds, the measurement systems must guarantee performance at least of this order. The choice of making digital a part or the totality of the measurement electronic systems exploits well-known advantages from the adaptivity, to the versatile calibration, to the easiness of implementation of powerful processing algorithms with lower power consumption, and area occupation with respect to the equivalent analog solutions. The last generation of digital programmable devices as Field Programmable Gate Arrays (FPGAs) and System-of-Chips (SoCs) has made possible the implementation of high-accuracy TDC architectures on programmable logic with performance comparable with ASIC realizations. In this way, all the well-known advantages of using programmable devices are exploited, such as totally tunable characteristics, easiness of portability, reduced time-to-market, lower migration cost from one generation of technology to another, just to name a few. This has to be done always keeping on foreground the maximum functional performance. The dissertation focuses on the maximization of sets of figures of merit single such as precision, resolution, full-scale range, power consumption, area occupancy, acquisition rate, depending on the target application. This is accomplished through measurement techniques like Nutt-interpolation and sub-interpolation algorithms, among which a high-performance totally new solution is presented in this dissertation. In particular, state-of-the-art of multi-channels sub-interpolated TDCs based on Tapped Delay-Line (TDL) and Nutt-interpolation are considered, both in terms of ideal and real features. Consequence of that is the introduction of a mathematical theory, new in literature, which explains and quantifies advantages and limits of this solution. Moreover, all investigated issues have been simulated and experimentally validated on a wide spectrum of devices from the Xilinx and Altera manufacturers. In this regard, the issue of migrating firmware between different devices has been studied by providing precise guidelines for the realization of TDC IP-Cores with timing performance comparable with ASIC solutions in the same technological node designed for being migrated between devices from the same or different manufacturers. As reference case study, is presented the implementation of a very high-performance (high-range, high-resolution and high-precision) multi-channel TDL-TDC (i.e. smart triggering of events, 16 channels, 12ps r.m.s. precision, 9.45s full-scale range with a resolution of 250fs) in devices of different manufacturers (i.e. Altera and Xilinx), paying particular attention to the migration of architectures in structurally very different devices This instrument is being used in several national (2) and international (5) research activities, among which a review of some as examples is presented. Moreover, the most significant achievements accomplished during the activity are attested by 39 international publications (8 on journal), of which 13 as first author and 1 single name submission.

diritti: info:eu-repo/semantics/closedAccess

Tesi di dottorato. | Lingua: en. | Paese: | BID: TD18091406